As integrated circuits (“IC”) have grown in complexity, the development and testing of circuits has become increasingly difficult and burdensome. Modern IC's may comprise transistors and the like that number into the millions, with a multiple of that number of connection wires. Different logical gate conditions will lead to different signal propagation through the IC, with the result that different IC operation permutations may exist for all possible gate condition combinations. When the number of gates numbers into the millions for circuits such as very large system integrations (“VLSI”), the number of permutations can be enormous. Also, the rapidly increasing operating speeds of circuits, some of which have currently crossed the gigahertz threshold, further complicate the modeling of circuits. Accordingly, accurate modeling of and analyzing the operation of modem circuits such as VLSI's can require computational resources that are so large as to be impractical.
Effective modeling of these circuits, however, can be a valuable tool in their design and manufacture. For example, in the design and manufacture of VLSI's, it is important to insure that the VLSI power distribution networks are of sufficiently low impedance in the VLSI. Excessive impedance can disadvantageously cause larger than expected local voltage drops along the power distribution network due to such factors as the resistance of metal layers used to carry the power signal and the amount of current flowing through them. Excessive impedance can cause large voltage variations in the driving signal as well as the surrounding distribution network that can ultimately lead to logic failures. Possible circuit failures can occur if the electrical impedance of even a local power distribution network is too high.
Modeling of circuit performance can be used to avoid these excessive impedance related problems. Under current methods, however, useful models of high speed VLSI's have proven exceedingly difficult and burdensome to accomplish. These models may require details of the specific logic being implemented and its connections to the power distribution network, the worst case switching behavior of all the signals and logic, and other detailed circuit data. An impedance evaluation of a VLSI incorporating all of this information could require development of a three-dimensional model and subsequent application of Maxwell's equations to the model. Such an approach would require extraordinary effort and computer resources.
Indeed, prior art computational tools providing such models have proven to be costly, cumbersome, and burdensome to use. Also, as these tools require knowledge of the worst case switching behavior, their use is generally limited to a relatively late stage in circuit design when detailed circuit logic is available. Any problems discovered at this late stage may be difficult to address as circuit changes may have wide ranging downstream effects. For these reasons, some prior art circuit design and analysis efforts did not use formal modeling tools to address power distribution impedance concerns, but instead relied on the “intuitive feel” of designers for network design. For modem circuits of appreciable complexity and size, with VLSI's being an example, this practice has proven unsatisfactory.
Unresolved needs in the art therefore exist.